Design of BPSK/QPSK Modulator using Verilog HDL and Matlab

Quadrature Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communication system and it’s because of its ability to transmit twice the data rate for a given bandwidth. In most cases, the QPSK modulator consumes less power and bandwidth in a modern devices but for a system like satellite and mobile devices where their operations are power limited, this is a problem that needs to be fixed. The objective is to design the QPSK modulator that uses less power for operation and it should be bandwidth efficient. The proposed technique uses data stored inside a memory block to produce a symbol according to the given input data. The QPSK modulation process requires a Direct Digital Synthesizer (DDS) to produce sine and cosine wave which are used as carrier signal with the data signal to produce QPSK/BPSK output signal. The proposed modulator successfully modeled with Verilog Hardware Description Language (HDL), simulated with Xilinx Integrated Software Environment (ISE) version 14.5 software. QPSK modulation is also performed on MATLAB tool, which gives three types of waveforms. 1) In-phase component, 2) Quadrature phase, and 3) Composite of both. After that the QPSK demodulator has been developed using MATLAB tool in order to verify the functionality of the modulator.